1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a non-laminate semiconductor package and method of forming a non-laminate semiconductor package.
2. Description of the Related Art
Current technology for the fabrication of semiconductor integrated circuit chip packages involves the use of a laminate materials such as glass fibers impregnated with a resin material such as BT (bismaleimide triazne), polyimide resins, or other organic resins. This type of conventional integrated circuit package has a chip or die positioned on one side of the laminate substrate and leads and/or solder balls on an opposite side of the substrate. The two sides of the substrate are electrically connected to one another by plated holes extending through the substrate called via holes.
One example of a known integrated circuit chip package is illustrated in FIG. 1. The package includes a laminate substrate 10 having a chip side 12 and an opposite mounting side 14. An integrated circuit chip 16 is mounted on the chip side 12 of the laminate substrate 10 and is connected by connecting wires 18 to a plurality of bond fingers 20 on the substrate. The bond fingers 20 are electrically connected to a plurality of via holes 22 which extend through the substrate 10 and electrically interconnect the chip side 12 of the substrate to the mounting side 14 of the substrate. On the mounting side 14 of the substrate 10, a plurality of solder balls 24 are positioned on solder pads 26 electrically connected to the via holes 22 by traces 28.
The via holes 22 used in the known integrated circuit chip packages are formed by drilling holes through the laminate substrate 10 and plating the holes with a conductive material such as copper. This method of forming the via holes 22 is both time-consuming and expensive. Thus, it would be desirable to replace the via holes 22 with a simpler and less expensive structure.
In addition, the laminate substrate 10 of the prior art generally includes about 40% glass fiber filler and about 60% resin. The large percentage of resin allows the laminate material to absorb moisture. The absorption of moisture causes substrate swelling and delamination of the components. In order to address the problems of moisture absorption and delamination, laminate substrates are preconditioned prior to use by exposure to moisture and heat for a substantial period of time, such as one week. This preconditioning process is both expensive and time-consuming.
In semiconductor chip fabrication, there is a continuing need to reduce package size while increasing electrical and thermal performance of the packages. The use of the via holes 22 in the known semiconductor chip package unnecessarily increases the overall size of the package because no traces or solder pads can be positioned at the locations of the via holes. For example, FIG. 2 illustrates a portion of a mounting side 14 of a known package having a plurality of solder balls 24, connected by traces 28 to the via holes 22 for electrical interconnection to the chip side 12 of the substrate. FIG. 3 illustrates the chip mounting side 12 of the package having a plurality traces 28 connecting the via holes 22 to the bond fingers 20. FIG. 4 shows the mounting side 14 superimposed on the chip side 12 with the chip side shown in hidden lines. As shown in FIG. 4, the solder balls 24 must be displaced from the via holes 22 and connected by traces, increasing the overall size of the package. Accordingly, it would be desirable to reduce the package size by moving the solder balls 24 closer to or directly over the via holes 22.
Another drawback of the known single sided and double sided semiconductor chip packages is the undercutting of the sides of the traces 28 and the solder pads 26 which occurs during etching due to the method in which the packages are produced.
The prior art chip packages are generally produced by a method such as the one illustrated in FIGS. 5A through 5E. The method of FIGS. 5A through 5E shows the formation of a single-sided substrate. The method includes the steps of providing a kapton tape carrier of polyamide 30 with a layer of copper foil 32 on one side as shown in FIG. 5A. As shown in FIG. 5B, a photo resist dry film 34 is laminated onto the surface of the copper foil 32 in a pattern in the shape of the various traces and pads to be formed in the copper foil. Alternatively, the photo resist pattern could be screen printed or the surface can be coated with a wet photo resist and dried. The copper foil 32 is then etched, as shown in FIG. 5C by a conventional etching process. However, the etching process tends to slightly undercut the copper material beneath the photo resist 34 providing angled sides of the traces and solder pads. The photo resist 34 is then striped from the copper traces and solder pads as illustrated in FIG. 5D resulting in a carrier 30 having a plurality of copper traces 28 and solder pads 26. Finally, the carrier 30 is mounted on a base 38 and a chip 16 is attached. The chip 16 may be placed in a cavity in the carrier 30 or the base 38. The chip 16 is connected by wires 18 to the traces 28 and then encapsulated with a molding or potting material 36. Solder balls 24 are placed on the solder pads 26 for mounting the package in an inverted or flip chip orientation.